Field of the Invention
The present invention relates to semiconductor devices, and particularly to voltage converters which generate an internal supply voltage used at least in some of the circuits of the semiconductor devices.
Moreover, it relates to voltage limiters for lowering an external supply voltage in semiconductor integrated circuit chips and impressing the lowered voltage on small geometry transistors in the chips, and particularly to voltage limiters enabling the attainment of stable output voltage in relation to an external supply voltage subject to a wide range of variation.
Description of the Prior Art
In recent years, there has been a problem of the lowering of breakdown voltage accompanying the scaling of semiconductor elements. Although this problem can be solved by lowering supply voltage, this solution is not always preferable for an external interface. Accordingly, it has been proposed to provide a method wherein an internal supply of a lower voltage (e.g. 3 V) than a supply voltage impressed from outside (e.g. 5 V in the case of TTL compatible chips) is prepared in a semiconductor device while the external supply voltage is left unvaried. As to a voltage converter for generating the internal supply from the external supply, a discussion is made, for instance, in Japanese Patent Laid-Open No. 111514/1984 (U.S. application Ser. No. 140,628). The circuit proposed in the aforesaid patent application is shown in FIG. 15(a). This circuit generates an internal supply V.sub.l from an external supply V.sub.CC. Element R denotes a resistance element, and BL.sub.0 and BL.sub.1 denote circuits which are called "unit circuits" in the aforesaid patent application. The "unit circuit" is so designed that a channel between B and C FIG. 15(b)) becomes non-continuous when a voltage between A and C is lower than a prescribed voltage (hereinafter called ON-voltage) while becoming continuous when said voltage is the prescribed voltage or above. FIG. 15(b) is an example of realization of the "unit circuit" described in the aforesaid application.
The characteristics of this circuit are shown in FIG. 15(c). When the external supply voltage V.sub.CC is V.sub.P0 (V.sub.P0 is the ON-voltage of the unit circuit BL.sub.0) or below, both BL.sub.0 and BL.sub.1 are in the non-continuous state, and therefore an output voltage V.sub.l is equal to V.sub.CC. When V.sub.CC exceeds V.sub.P0, BL.sub.0 turns to be in continuity, and therefore V.sub.l is determined by the ratio between the resistance element R and the ON-voltage of BL.sub.0. Accordingly the V.sub.CC dependency (inclination m) of V.sub.l is smaller than 1 as shown in the figure. When V.sub.CC rises and a difference V.sub.CC -V.sub.l exceeds V.sub.P1 (V.sub.P1 is the ON-voltage of the unit circuit BL.sub.1), moreover, BL.sub.1 turns to be in continuity, and the ON-resistance R.sub.1 of BL.sub.1 is connected in parallel to the resistance R. Accordingly, the V.sub.CC dependency of V.sub.l (inclination m') becomes larger than m.
For the V.sub.CC dependency of V.sub.l, characteristics bent at points P and P' are obtained. Values of V.sub.CC at the points P and P' are ##EQU1## The inclinations m and m' are ##EQU2##
The present circuit is advantageous in that it enables the voltage aging of a circuit operated by the internal supply V.sub.l (hereinafter abbreviated as an internal circuit), as will be described below. The voltage aging is a technique wherein a voltage higher than the one applied in ordinary operation is impressed on a supply terminal before delivery of semiconductor devices so as to exclude therefrom those devices which become imperfect after the voltage is applied, and it is effective for reducing initial imperfections after the delivery. In order to enable the voltage aging of the internal circuit, it is only required to design V.sub.0 and V.sub.0 ' so that the external supply voltage V.sub.CC in ordinary operation be found between V.sub.0 and V.sub.0 ' and that V.sub.CC in aging be higher than V.sub.0 '. By such a design as stated above, the operation of the internal circuit is made stable in ordinary operation even when V.sub.CC varies, since the V.sub.CC dependency m of V.sub.l is small therein. On the other hand, V.sub.l higher sufficienctly than in ordinary operation is impressed on the internal circuit in aging and thereby the voltage aging of the internal circuit is implemented, since the V.sub.CC dependency m' of V.sub.l is large in aging.
A problem of the above-described prior art is that the characteristics of internal supply in ordinary operation and the characteristics thereof in aging can not be designed independent of each other. In the circuit of FIG. 15(a), for instance, the characteristics in ordinary operation are determined by BL.sub.0, and those in aging by BL.sub.0 and BL.sub.1. When BL.sub.0 is altered to modify the characteristics in ordinary operation, therefore, the characteristics in aging are also modified simultaneously. The parameters m' and V.sub.0 ' determining the characteristics in aging are expressed as ##EQU3## according to equations (1) to (4). As is apparent from these equations, the parameters m' and V.sub.0 ' determining the characteristics in aging are dependent on m and V.sub.0 which are parameters determining the characteristics in ordinary operation. Accordingly, it is necessary to redesign BL.sub.1 every time when the characteristics in ordinary operation are modified.
FIG. 26 shows a prior-art voltage limiter circuit and an example an application thereof. This example is described in the Extended Abstracts of the 18th Conference on Solid State Devices and Materials, 1896, pp. 307-310.
The operation thereof will be summarized in the following. In the figure, numeral 1 denotes a semiconductor chip of a voltage generator, VC2 a feedback type voltage limiter circuit formed of a differential amplifier, and L1 and L3 circuits comprising small geometry transistors whose breakdown voltage is low. These circuits are the loads of said voltage limiter circuit, for instance. Mark L2 denotes a circuit comprising a transistor whose size is large and whose breakdown voltage is high. Voltages VLO.sub.1 and VLO.sub.2 made lower than an external voltage V.sub.CC by the voltage limiter with limiter reference voltages VL1 and VL2 used as references are impressed on L1 and L3, respectively. Meanwhile, V.sub.CC is impressed directly on L2. Marks .phi..sub.1, .phi..sub.2 and .phi..sub.3 denote driving signals for L1, L2 and L3 respectively. .phi..sub.1 ' and .phi..sub.3 ' are signals controlling a current of the differential amplifier in the voltage limiter VC2 and turning a transistor Q.sub.8 ON and OFF. These signals are varied from High level (V.sub.CC) to Low level (V.sub.SS) at a time point when L1 and L3 start operations in response to .phi..sub.1 and .phi..sub.3 '. Thereby the transistor Q.sub.8 in VC2 is turned. ON and the current of the differential amplifier is increased, so that it can respond at high speed to fluctuations of VLO.sub.1 and VLO.sub.2 due to current fluctuations of L1 and L3. When L1 and L3 do not operate, on the other hand, said signals are made to be at High level and thereby Q.sub.8 is cut off. Thereby the current flowing through the differential amplifier turns to have a value obtained only by Q.sub.9. By setting g.sub.m of Q.sub.8 to be large and g.sub.m of Q.sub.9 to be small, accordingly, a voltage limiter operating at high speed and consuming low power can be realized.
Besides, VC2 comprises two circuits connected to separate loads respectively in the figure, and 10 this is to prevent the fluctuation of an internal supply voltage due to the current fluctuation of one load from affecting the other load.
According to the above-described prior art, the differential amplifier employed in the voltage limiter circuit is so constructed, as shown in FIG. 26, that the P-channel transistors Q.sub.8 and Q.sub.9 are used as common source loads, N-channel transistors Q.sub.12 and Q.sub.13 as active loads and P-channel transistors Q.sub.10 and Q.sub.11 as a source-coupled pair and a reference voltage and a limiter output voltage are inputted directly to the gates thereof. In such a construction as described above, however, a gate-source voltage V.sub.GS of the source-coupled pair depends on a difference voltage between V.sub.CC and VL or VLO, since Q.sub.8 and Q.sub.9 make the same operations as resistances in a non-saturation region. When the difference between V.sub.CC and VL becomes small, in other words, when V.sub.CC turns low or VL turns high, therefore, V.sub.GS becomes small and a current lessens, which results in the slowdown of a response speed. In the condition of V.sub.CC .ltoreq.VL+V.sub.T, besides, there occurs a problem that Q.sub.10 and Q.sub.11 are cut off (discontinue operating as the amplifier). V.sub.T is an absolute value of the threshold voltage of the transistors Q.sub.10 and Q.sub.11.
When VL=3(V) and V.sub.T =1(V) are substituted as general numerical values in the above expression, then V.sub.CC .ltoreq.4(V), and so the circuit does not operate if V.sub.CC is a voltage of 4(V) or below. In order to secure operations against the drop of a supply voltage due to a spike current or the like, DRAM for products or the like needs to be so designed as to operate with a voltage as low as V.sub.CC =3 V approximately. DRAM or the like according to a prior-art system does not operate below V.sub.CC =4 V, in this relation, and therefore the present circuit is not suitable for practical use.
In addition, the current of the differential amplifier is controlled only at two stages, stages of standby and operation, in the prior art. Moreover, the signal used therefor is not generated on the basis of direct detection of the state of a load, but generated in response to a load driving signal or a clock signal given before or behind said signal. Therefore the current of the differential amplifier needs to be kept large for a longer time than a time required for completion of the operation of the load. Consequently, power consumption is not reduced sufficiently.